From d35c7fe1bff55471c62b11d208cf3a71dec30d6d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 30 Oct 2018 07:07:00 +0100 Subject: amd/mtrr: Fix IORR MTRR IORR MTRR definitions renamed to avoid collision between and . Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 8b6a8d41bc..7920e656f5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2148,10 +2148,10 @@ void SetTargetWTIO_D(u32 TestAddr) u32 lo, hi; hi = TestAddr >> 24; lo = TestAddr << 8; - _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ + _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */ hi = 0xFF; lo = 0xFC000800; /* 64MB Mask */ - _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ + _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */ } void ResetTargetWTIO_D(void) @@ -2160,7 +2160,7 @@ void ResetTargetWTIO_D(void) hi = 0; lo = 0; - _WRMSR(0xc0010017, lo, hi); /* IORR0 Mask */ + _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */ } u32 SetUpperFSbase(u32 addr_hi) -- cgit v1.2.3