From bc5ad1087b571f22181f7d3edc91354c03269fbf Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sat, 12 Mar 2016 17:17:23 -0600 Subject: nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a did not take into account the default UI setting introduced in change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM instability and occassional failure to boot. Use the correct 1UI value for the modified function semantics. Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/14073 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Paul Menzel Reviewed-by: Martin Roth --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 182fab040e..15b5ea4fcb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1703,7 +1703,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20 << 1; + current_read_dqs_delay[internal_lane] = 0x20; write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); /* Calculate and program MaxRdLatency */ -- cgit v1.2.3