From 471f103e530b97c1125acdab259043dd7f252fe9 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 3 Jun 2011 19:59:52 +0000 Subject: This patch sets max freq defaults for ddr2 and ddr3for fam10. Signed-off-by: Marc Jones Acked-by: Scott Duplichan git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 0894b3f88d..1191536234 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1315,7 +1315,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, u16 word; /* Get CPU Si Revision defined limit (NPT) */ - proposedFreq = 533; /* Rev F0 programmable max memclock is */ + proposedFreq = 800; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { -- cgit v1.2.3