From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/northbridge/amd/amdmct/mct/mct_d.c | 16 ++++++++-------- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 7 ++++--- src/northbridge/amd/amdmct/mct/mctsrc.c | 7 ++++--- src/northbridge/amd/amdmct/mct/mcttmrl.c | 7 ++++--- 4 files changed, 20 insertions(+), 17 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct') diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 4267e6d07c..2488dfc22b 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -33,9 +33,9 @@ * supported. */ -#include "mct_d.h" - #include +#include +#include "mct_d.h" static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -3686,7 +3686,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); lo |= 1 << ClLinesToNbDis; _WRMSR(msr, lo, hi); @@ -3703,7 +3703,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG2; + msr = BU_CFG2_MSR; _RDMSR(msr, &lo, &hi); if (!pDCTstat->ClToNB_flag) lo &= ~(1 << ClLinesToNbDis); @@ -3721,7 +3721,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi |= (1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3737,7 +3737,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, // FIXME: Maybe check the CPUID? - not for now. // pDCTstat->LogicalCPUID; - msr = BU_CFG; + msr = BU_CFG_MSR; _RDMSR(msr, &lo, &hi); hi &= ~(1 << WbEnhWsbDis_D); _WRMSR(msr, lo, hi); @@ -3845,7 +3845,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, return; } - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; @@ -3877,7 +3877,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } if (!wrap32dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 9bb87bbb2a..39c11ce7da 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -13,9 +13,10 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include #include +#include "mct_d.h" static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u16 like, @@ -286,7 +287,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { _Wrap32Dis = 1; @@ -368,7 +369,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat, mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index a29f8eb42e..4689c7b982 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -14,8 +14,9 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include +#include "mct_d.h" /****************************************************************************** Description: Receiver En and DQS Timing Training feature for DDR 2 MCT @@ -170,7 +171,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, write_cr4(cr4); print_t("TrainRcvrEn: 2\n"); - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); //FIXME: Why use SSEDIS if (lo & (1 << 17)) { /* save the old value */ @@ -443,7 +444,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - msr = HWCR; + msr = HWCR_MSR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index 4c6d8e6fee..192288a2c4 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -13,8 +13,9 @@ * GNU General Public License for more details. */ -#include "mct_d.h" #include +#include +#include "mct_d.h" /* * Description: Max Read Latency Training feature for DDR 2 MCT @@ -132,7 +133,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; @@ -182,7 +183,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, } if (!_Wrap32Dis) { - addr = HWCR; + addr = HWCR_MSR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); -- cgit v1.2.3