From 362db613a0556a102e2812c1c00e3491eafdb66f Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Thu, 8 Apr 2010 15:12:18 +0000 Subject: Cosmetically make init_cpus more similar for fam10 and K8. Remove some fam10 warnings. Signed-off-by: Myles Watson Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdmct/mct/mct_d.h | 11 +++++++---- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 4 ++-- src/northbridge/amd/amdmct/mct/mctpro_d.c | 13 +++---------- src/northbridge/amd/amdmct/mct/mctsrc.c | 4 ++-- 4 files changed, 14 insertions(+), 18 deletions(-) (limited to 'src/northbridge/amd/amdmct/mct') diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 9542bcb045..148f987023 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -726,13 +726,16 @@ int mctRead_SPD(u32 smaddr, u32 reg); void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); +void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass); -static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request); -static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_Wait(u32 cycles); +u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct); +u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly); +void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request); +u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); +void mct_Wait(u32 cycles); u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel); u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); +void EarlySampleSupport_D(void); #endif diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 9dfccd9c4e..170760ddfe 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -582,8 +582,8 @@ skipLocMiddle: } -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) +void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 ChipSel) { /* Store the DQSDelay value, found during a training sweep, into the DCT * status structure for this node diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index 8087c1c058..961d1f5771 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct); -static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly); - void EarlySampleSupport_D(void) { } - u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) { u32 tmp; @@ -251,7 +246,7 @@ void SyncSetting(struct DCTStatStruc *pDCTstat) } -static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) +u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) { u32 ret = 0; u32 lo, hi; @@ -362,7 +357,7 @@ static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, } -static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) +u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) { u8 skip = 0; @@ -393,8 +388,7 @@ static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr) return 0; } - -static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { +void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { /* Erratum #202: disable DCache scrubber for Ax parts */ @@ -403,4 +397,3 @@ static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } - diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 7b5e1b4b54..0c2a08f8ce 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -502,7 +502,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, } -static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) +u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { if (pDCTstat->DIMMValidDCT[dct] == 0 ) { return 8; @@ -1080,7 +1080,7 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat, } -static void mct_Wait(u32 cycles) +void mct_Wait(u32 cycles) { u32 saved; u32 hi, lo, msr; -- cgit v1.2.3