From 7e9de01c4758cc1e8adb05d0c443701495e98fe0 Mon Sep 17 00:00:00 2001 From: Florian Zumbiehl Date: Tue, 1 Nov 2011 20:17:12 +0100 Subject: Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl Reviewed-on: http://review.coreboot.org/370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdk8') diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b7ed..dc3addbe87 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; -- cgit v1.2.3