From 20f25dd5c8a513ee136e9f6d8c67959591298617 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 22 Apr 2014 10:41:05 -0700 Subject: Rename coreboot_ram stage to ramstage Rename coreboot_ram stage to ramstage. This is done in order to provide consistency with other stage names (bootblock, romstage) and to allow any Makefile rule generalization, required for patches to be submitted later. Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386 Signed-off-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/5567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdk8') diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index e5bcdcb9c1..a4943bd2b9 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -80,7 +80,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * pci1234[0] will record the south bridge link and bus range * pci1234[i] will record HT chain i. * - * For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT + * For example, on the Tyan S2885 ramstage will put the AMD8151 chain (HT * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the * register 0xE4. * -- cgit v1.2.3