From 15279a9696c70b82c2223264a505da9122f9aa7b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:05:26 +0200 Subject: src/northbridge: Capitalize CPU, RAM and ROM Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdk8/coherent_ht.c | 6 +++--- src/northbridge/amd/amdk8/early_ht.c | 2 +- src/northbridge/amd/amdk8/f.h | 2 +- src/northbridge/amd/amdk8/incoherent_ht.c | 4 ++-- src/northbridge/amd/amdk8/raminit.c | 6 +++--- src/northbridge/amd/amdk8/raminit_f.c | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/northbridge/amd/amdk8') diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8779ec7c7b..a7c3fc27c6 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) static void disable_probes(void) { /* disable read/write/fill probes for uniprocessor setup - * they don't make sense if only one cpu is available + * they don't make sense if only one CPU is available */ /* Hypetransport Transaction Control Register @@ -1597,7 +1597,7 @@ static void coherent_ht_finalize(unsigned nodes) } #endif - /* set up cpu count and node count and enable Limit + /* set up CPU count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range * registers on Hammer A0 revision. @@ -1622,7 +1622,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif pci_write_config32(dev, 0x60, val); - /* Only respond to real cpu pci configuration cycles + /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b1f5..1bc34e42f1 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -8,7 +8,7 @@ static void enumerate_ht_chain(void) /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index af4658dd8e..f83282bfeb 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -535,7 +535,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if(sysinfo->nodes == 1) return; // in case only one CPU installed for(i=1; inodes; i++) { /* Skip everything if I don't have any memory on this controller */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d765fc7003..12b8290dd1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -481,7 +481,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ @@ -631,7 +631,7 @@ static int ht_setup_chains(uint8_t ht_c_num) #endif { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index fbcb8879f8..f502287d22 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -859,7 +859,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1243,7 +1243,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; @@ -2476,7 +2476,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //FIXME add enable node interleaving here -- yhlu /*needed? - 1. check how many nodes we have , if not all has ram installed get out + 1. check how many nodes we have , if not all has RAM installed get out 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index cd4b9fbf52..8ed0335703 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; -- cgit v1.2.3