From 9a791dffeae2097aa0a18f645ce07acfed41b9bc Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Mon, 3 Apr 2006 20:38:34 +0000 Subject: new cache_as_ram support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/reset_test.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'src/northbridge/amd/amdk8/reset_test.c') diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index e60447c2ff..932b807b45 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -51,3 +51,37 @@ static void set_bios_reset(void) htic &= ~HTIC_BIOSR_Detect; pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + unsigned reg; + + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + unsigned config_map; + config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + if ((config_map & 3) != 3) { + continue; + } + if ((((config_map >> 4) & 7) == node) && + (((config_map >> 8) & 3) == link)) + { + return (config_map >> 16) & 0xff; + } + } + return 0; +} + +static unsigned get_sblk(void) +{ + uint32_t reg; + /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + return ((reg>>8) & 3) ; +} + +static unsigned get_sbbusn(unsigned sblk) +{ + return node_link_to_bus(0, sblk); +} + + -- cgit v1.2.3