From 2c018fba95a5f40c4eaaa20421e8c893dffdb62e Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Mon, 21 Jul 2003 20:13:45 +0000 Subject: - First pass at s2880 support. - SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/reset_test.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/northbridge/amd/amdk8/reset_test.c') diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 949bd7cc15..ab48f9830e 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -34,10 +34,12 @@ static int cpu_init_detected(void) return cpu_init; } -static void distinguish_cpu_resets(void) +static void distinguish_cpu_resets(unsigned node_id) { uint32_t htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + device_t device; + device = PCI_DEV(0, 0x18 + node_id, 0); + htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_write_config32(device, HT_INIT_CONTROL, htic); } -- cgit v1.2.3