From 23202a9870a76c45fdd57771aa5546ebedf649b3 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Wed, 5 Jan 2005 20:29:05 +0000 Subject: enable apic ext id git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/reset_test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/northbridge/amd/amdk8/reset_test.c') diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 0663967b07..e60447c2ff 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -7,12 +7,12 @@ #define HTIC_BIOSR_Detect (1<<5) #define HTIC_INIT_Detect (1<<6) -static int cpu_init_detected(void) +static int cpu_init_detected(unsigned nodeid) { unsigned long htic; device_t dev; - dev = PCI_DEV(0, 0x18 + lapicid(), 0); + dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); return !!(htic & HTIC_INIT_Detect); @@ -34,11 +34,11 @@ static int cold_reset_detected(void) return !(htic & HTIC_ColdR_Detect); } -static void distinguish_cpu_resets(void) +static void distinguish_cpu_resets(unsigned nodeid) { uint32_t htic; device_t device; - device = PCI_DEV(0, 0x18 + lapicid(), 0); + device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; pci_write_config32(device, HT_INIT_CONTROL, htic); -- cgit v1.2.3