From b03b33697d44fb4140922d47a4df1edd25a40a74 Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 17 Jul 2003 06:34:30 +0000 Subject: - Update Config so we now have the proper number of cpus - Remove some debugging code from auto.c - Update coeherent_ht.c so we get the proper broadcast routes. - Fix the dram probing code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdk8/coherent_ht.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/northbridge/amd/amdk8/coherent_ht.c') diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 516f0fc6ae..5c11991646 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -526,8 +526,8 @@ static unsigned int generate_row(u8 node, u8 row, u8 maxnodes) u32 ret=DEFAULT; static const unsigned int rows_2p[2][2] = { - { 0x00030101, 0x00010404 }, - { 0x00010404, 0x00030101 } + { 0x00050101, 0x00010404 }, + { 0x00010404, 0x00050101 } }; static const unsigned int rows_4p[4][4] = { @@ -622,9 +622,11 @@ static void setup_remote_node(u8 node, u8 cpus) uint32_t value; uint8_t reg; reg = pci_reg[i]; +#if 0 print_debug("copying reg: "); print_debug_hex8(reg); print_debug("\r\n"); +#endif value = pci_read_config32(NODE_MP(0), reg); pci_write_config32(NODE_MP(7), reg, value); -- cgit v1.2.3