From 6276b6f151e050f0470fa7f1c5a2d73ff3f65282 Mon Sep 17 00:00:00 2001 From: Xavi Drudis Ferran Date: Mon, 28 Feb 2011 03:35:43 +0000 Subject: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn are reserved for revisions D0 and earlier, so whe should not set them to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change. For revisions > D0 (when we support them) it is ok not ot clear them, because they are documented as 0 on reset. bit 12 should be left alone according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask too, just to indicate we're touching them ? We'll OR them to 1111 anyway... Signed-off-by: Xavi Drudis Ferran Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdht/AsPsDefs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/amd/amdht') diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index dd59496c49..b961ac5aa7 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -111,7 +111,7 @@ #define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */ #define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/ -#define CPTC0_MASK 0x000c0fff /* Reset mask for this register */ +#define CPTC0_MASK 0x000cffff /* Reset mask for this register */ #define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */ #define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */ #define NB_FID_EN 0x20 /* NbFidEn bit ON */ -- cgit v1.2.3