From fdf31cb9d9dab81817463512a9159f0bdb568339 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 7 Aug 2015 19:05:45 -0500 Subject: northbridge/amd/amdht: Add comment for HT Freq write ordering The BKDG is not correct regarding HT Freq write ordering; indicate this in a comment to avoid confusion. Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12030 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdht/h3ncmn.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/northbridge/amd/amdht/h3ncmn.c') diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 29524afee0..c97d59293f 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1555,6 +1555,10 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) } else { temp2 = 0x0; } + /* NOTE + * The Family 15h BKDG Rev. 3.14 is wrong + * Freq[4] must be set before Freq[3:0], otherwise the register writes will be ignored! + */ if (is_gt_rev_d()) AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); -- cgit v1.2.3