From a813160fbc37c41451afa01667669cf81b5799e7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 19 Sep 2016 10:27:57 -0600 Subject: northbridge/amd: Improve code formatting Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/amd/amdht/h3ncmn.c | 46 +++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 23 deletions(-) (limited to 'src/northbridge/amd/amdht/h3ncmn.c') diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cbe90e03e2..0d0055b4f6 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -352,11 +352,11 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * @param[in] link = the link on that Node to examine * @param[in] *nb = this northbridge * @return true - The link has the following status - * linkCon=1, Link is connected - * InitComplete=1, Link initialization is complete - * NC=0, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * linkCon = 1, Link is connected + * InitComplete = 1, Link initialization is complete + * NC = 0, Link is coherent + * UniP-cLDT = 0, Link is not Uniprocessor cLDT + * LinkConPend = 0 Link connection is not pending * false- The link has some other status * *****************************************************************************/ @@ -375,7 +375,7 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) /* FN0_98/A4/C4 = LDT Type Register */ AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType); - /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */ + /* Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0 */ return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT; #else return 0; @@ -612,7 +612,7 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) CPU_NB_FUNC_03, REG_NB_DOWNCORE_3X190), 3, 0, &leveling); - for (i=0; imaxLinks; i++) + for (i = 0; i < nb->maxLinks; i++) { temp = 0; if (nb->verifyLinkIsCoherent(node, i, nb)) { temp = 0x26; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } else @@ -2102,7 +2102,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (nb->verifyLinkIsNonCoherent(node, i, nb)) { temp = 0x25; - ASSERT(i<3); + ASSERT(i < 3); AmdPCIWriteBits(currentPtr, 8*i + 5, 8*i, &temp); } } @@ -2142,7 +2142,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * Errata 153 applies to JH-1, JH-2 and older. It is fixed in JH-3 * (and, one assumes, from there on). */ - for (i=0; i < (pDat->NodesDiscovered +1); i++) + for (i = 0; i < (pDat->NodesDiscovered +1); i++) { AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(i), makePCIBusFromNode(i), @@ -2158,7 +2158,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } } - for (i=0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) + for (i = 0; i < CPU_ADDR_NUM_CONFIG_MAPS; i++) { isOuter = FALSE; /* Check for outer node by scanning the config maps on node 0 for one @@ -2179,7 +2179,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (node == (u8)temp) { /* This is an outer node. Tune it appropriately. */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (isErrata153) { @@ -2218,7 +2218,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) if (isErrata153) { /* Tuning for inner node coherent links */ - for (j=0; j < nb->maxLinks; j++) + for (j = 0; j < nb->maxLinks; j++) { if (nb->verifyLinkIsCoherent(node, j, nb)) { -- cgit v1.2.3