From e485aa496b2230226abf2255837b9e1d422e9b42 Mon Sep 17 00:00:00 2001 From: Xavi Drudis Ferran Date: Mon, 28 Feb 2011 02:33:59 +0000 Subject: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Contemplate the possibility of nbCofVidUpdate not being defined, trying to get closer to BKDG Signed-off-by: Xavi Drudis Ferran Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/amd/amdht/AsPsDefs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/amd/amdht/AsPsDefs.h') diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 3907208290..0f6db9fc75 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -229,6 +229,8 @@ /* F3x1F0 Product Information Register */ #define NB_PSTATE_MASK 0x00070000 /* NbPstate for CPU rev C3 */ +/* F3x1FC Product Information Register */ +#define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */ #define NM_PS_REG 5 /* number of P-state MSR registers */ -- cgit v1.2.3