From feed329a0c006968242aa3065506b5f37f4308d4 Mon Sep 17 00:00:00 2001 From: Kerry She Date: Thu, 18 Aug 2011 18:03:44 +0800 Subject: AMD F14 southbridge update This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Signed-off-by: Kerry She Signed-off-by: Kerry She Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/amdfam10/northbridge.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/northbridge/amd/amdfam10') diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c64747403d..89bd6733ce 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -47,6 +47,9 @@ #endif #include +#if CONFIG_AMD_SB_CIMX +#include +#endif struct amdfam10_sysconf_t sysconf; @@ -1445,6 +1448,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Mid_Post_Init(); +#endif } static void cpu_bus_noop(device_t dev) -- cgit v1.2.3