From 16ff807ba6444a0eea02c8929b73a5c3701ec16d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 11 Dec 2015 12:58:07 -0600 Subject: amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12712 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/amd/amdfam10/northbridge.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/northbridge/amd/amdfam10') diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c8bf8fab52..58507d0866 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -737,16 +737,16 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; -- cgit v1.2.3