From 04f8fd981fd49e9929fea2b27991e78673fc57a3 Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Mon, 19 Sep 2016 10:24:34 -0600
Subject: northbridge/amd/amdfam10: Improve code formatting

Change-Id: I86a252598666af635281eaa467020acb53d71c77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/northbridge/amd/amdfam10/acpi.c                | 24 +++++++++---------
 src/northbridge/amd/amdfam10/amdfam10.h            |  6 ++---
 src/northbridge/amd/amdfam10/amdfam10_util.asl     | 18 +++++++-------
 src/northbridge/amd/amdfam10/debug.c               | 12 ++++-----
 src/northbridge/amd/amdfam10/early_ht.c            |  4 +--
 src/northbridge/amd/amdfam10/get_pci1234.c         |  8 +++---
 src/northbridge/amd/amdfam10/ht_config.c           | 24 +++++++++---------
 src/northbridge/amd/amdfam10/northbridge.c         | 29 +++++++++++-----------
 src/northbridge/amd/amdfam10/raminit.h             |  4 +--
 src/northbridge/amd/amdfam10/raminit_amdmct.c      |  8 +++---
 .../amd/amdfam10/raminit_sysinfo_in_ram.c          |  4 +--
 src/northbridge/amd/amdfam10/reset_test.c          |  4 +--
 src/northbridge/amd/amdfam10/setup_resource_map.c  |  4 +--
 13 files changed, 74 insertions(+), 75 deletions(-)

(limited to 'src/northbridge/amd/amdfam10')

diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index 51da7d6c88..e67a127cf4 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -96,7 +96,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
 	 */
 	if ((basek+sizek)<1024) return;
 
-	if (basek<1024) {
+	if (basek < 1024) {
 		sizek -= 1024 - basek;
 		basek = 1024;
 	}
@@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current)
 	*p = (u8) nodes;
 	p += 8;
 
-	for (i=0;i<nodes;i++) {
-		for (j=0;j<nodes; j++) {
-			if (i==j)
+	for (i = 0; i < nodes; i++) {
+		for (j = 0; j < nodes; j++) {
+			if (i == j)
 				p[i*nodes+j] = 10;
 			else
 				p[i*nodes+j] = 16;
@@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_name("BUSN");
 	acpigen_write_package(HC_NUMS);
-	for (i=0; i<HC_NUMS; i++) {
+	for (i = 0; i < HC_NUMS; i++) {
 		acpigen_write_dword(sysconf.ht_c_conf_bus[i]);
 	}
 	// minus the opcode
@@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_NUMS * 4);
 
-	for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
+	for (i = 0; i<(HC_NUMS*2); i++) { // FIXME: change to more chain
 		acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base
 		acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask
 	}
@@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_NUMS * 2);
 
-	for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
+	for (i = 0; i < HC_NUMS; i++) { // FIXME: change to more chain
 		acpigen_write_dword(sysconf.conf_io_addrx[i]);
 		acpigen_write_dword(sysconf.conf_io_addr[i]);
 	}
@@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_POSSIBLE_NUM);
 
-	for (i=0;i<sysconf.hc_possible_num;i++) {
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
 		acpigen_write_dword(sysconf.pci1234[i]);
 	}
-	for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+	for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
 		acpigen_write_dword(0x00000000);
 	}
 	// minus the opcode
@@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_POSSIBLE_NUM);
 
-	for (i=0;i<sysconf.hc_possible_num;i++) {
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
 		acpigen_write_dword(sysconf.hcdn[i]);
 	}
-	for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+	for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
 		acpigen_write_dword(0x20202020);
 	}
 	// minus the opcode
@@ -311,7 +311,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_name_byte("CBST", CBST);
 
-	if ((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
+	if ((CONFIG_CBB == 0xff) && (sysconf.nodes > 32)) {
 		 CBS2 = 0x0f;
 		 CBB2 = (u8)(CONFIG_CBB-1);
 	} else {
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 4c3aec60eb..2ef22ee4d1 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -967,8 +967,8 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 #include "nums.h"
 
 #ifdef __PRE_RAM__
-#if NODE_NUMS==64
-	 #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#if NODE_NUMS == 64
+	 #define NODE_PCI(x, fn) ((x < 32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
 #else
 	 #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
 #endif
@@ -977,7 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 #include "raminit.h"
 
 #include "../amdmct/wrappers/mcti.h"
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
   #include "../amdmct/mct_ddr3/mct_d.h"
 #else
   #include "../amdmct/mct/mct_d.h"
diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl
index bf0d177e14..6e2118d1ae 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.asl
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl
@@ -56,9 +56,9 @@ Scope (\_SB)
 
 	Method (DADD, 2, NotSerialized)
 	{
-		Store( Arg1, Local0)
-		Store( Arg0, Local1)
-		Add( ShiftLeft(Local1,16), Local0, Local0)
+		Store(Arg1, Local0)
+		Store(Arg0, Local1)
+		Add(ShiftLeft(Local1,16), Local0, Local0)
 		Return (Local0)
 	}
 
@@ -66,7 +66,7 @@ Scope (\_SB)
 	Method (GHCE, 1, NotSerialized) // check if the HC enabled
 	{
 		Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
-		if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+		if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) }
 		Else { Return (0x00) }
 	}
 
@@ -74,7 +74,7 @@ Scope (\_SB)
 	{
 		Store (0x00, Local0)
 		Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
-		Store (ShiftRight( And (Local1, 0xfc), 0x02), Local0)
+		Store (ShiftRight(And (Local1, 0xfc), 0x02), Local0)
 		Return (Local0)
 	}
 
@@ -82,7 +82,7 @@ Scope (\_SB)
 	{
 		Store (0x00, Local0)
 		Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
-		Store (ShiftRight( And (Local1, 0x700), 0x08), Local0)
+		Store (ShiftRight(And (Local1, 0x700), 0x08), Local0)
 		Return (Local0)
 	}
 
@@ -92,7 +92,7 @@ Scope (\_SB)
 		Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
 		Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
 		Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
-		Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+		Store (And (ShiftRight(Local1, Local2), 0xff), Local0)
 		Return (Local0)
 	}
 
@@ -176,7 +176,7 @@ Scope (\_SB)
 		Store (0x00, Local0)
 		Store (0x00, Local4)
 		Store (0x00, Local3)
-		While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem ) *2 ( base, limit )
+		While (LLess (Local0, 0x80)) // 0x20 links * 2(mem, prefmem) *2 (base, limit)
 		{
 			Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
 			Increment (Local0)
@@ -237,7 +237,7 @@ Scope (\_SB)
 		Store (0x00, Local0)
 		Store (0x00, Local4)
 		Store (0x00, Local3)
-		While (LLess (Local0, 0x40)) // 0x20 ht links * 2 ( base, limit)
+		While (LLess (Local0, 0x40)) // 0x20 ht links * 2 (base, limit)
 		{
 			Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
 			Increment (Local0)
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index e01c44deea..327a0e68e3 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -95,7 +95,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
 			printk(BIOS_DEBUG, "\n%04x:",i);
 		}
 		val = pci_read_config32(dev, i);
-		for (j=0;j<4;j++) {
+		for (j = 0; j < 4; j++) {
 			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
@@ -121,7 +121,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 		int j;
 		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
-		for (j=0;j<4;j++) {
+		for (j = 0; j < 4; j++) {
 			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
@@ -262,7 +262,7 @@ static void dump_smbus_registers(void)
 	printk(BIOS_DEBUG, "\n");
 	for (device = 1; device < 0x80; device++) {
 		int j;
-		if ( smbus_read_byte(device, 0) < 0 ) continue;
+		if (smbus_read_byte(device, 0) < 0) continue;
 		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for (j = 0; j < 256; j++) {
 			int status;
@@ -287,7 +287,7 @@ static inline void dump_io_resources(u32 port)
 	int i;
 	udelay(2000);
 	printk(BIOS_DEBUG, "%04x:\n", port);
-	for (i=0;i<256;i++) {
+	for (i = 0; i < 256; i++) {
 		u8 val;
 		if ((i & 0x0f) == 0) {
 			printk(BIOS_DEBUG, "%02x:", i);
@@ -305,8 +305,8 @@ static inline void dump_mem(u32 start, u32 end)
 {
 	u32 i;
 	printk(BIOS_DEBUG, "dump_mem:");
-	for (i=start;i<end;i++) {
-		if ((i & 0xf)==0) {
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
 			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
 		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index a1b411f606..812935e108 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -96,7 +96,7 @@ static void enumerate_ht_chain(void)
 					pci_devfn_t devx;
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-					if (next_unitid>=0x18) {
+					if (next_unitid >= 0x18) {
 						if (!end_used) {
 							next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
 							end_used = 1;
@@ -158,7 +158,7 @@ static void enumerate_ht_chain(void)
 
 out:	;
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
-	if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
+	if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
 		u16 flags;
 		flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
 		flags &= ~0x1f;
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index a6f679ecad..11f1589251 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -73,7 +73,7 @@ void get_pci1234(void)
 	//2. so at the same time we need update hsdn with hcdn_reg here
 //	printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
 
-	for (j=0;j<sysconf.ht_c_num;j++) {
+	for (j = 0; j < sysconf.ht_c_num; j++) {
 		u32 dwordx;
 		dwordx = sysconf.ht_c_conf_bus[j];
 //		printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
@@ -86,7 +86,7 @@ void get_pci1234(void)
 		if ((dwordx & 1)) {
 			// We need to find out the number of HC
 			// for exact match
-			for (i=1;i<sysconf.hc_possible_num;i++) {
+			for (i = 1; i < sysconf.hc_possible_num; i++) {
 				if ((dwordx & 0x7fc) == (sysconf.pci1234[i] & 0x7fc)) { // same node and same linkn
 					sysconf.pci1234[i] = dwordx;
 					sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -94,7 +94,7 @@ void get_pci1234(void)
 				}
 			}
 			// for 0xffc match or same node
-			for (i=1;i<sysconf.hc_possible_num;i++) {
+			for (i = 1; i < sysconf.hc_possible_num; i++) {
 				if ((dwordx & 0x7fc) == (dwordx & sysconf.pci1234[i] & 0x7fc)) {
 					sysconf.pci1234[i] = dwordx;
 					sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -104,7 +104,7 @@ void get_pci1234(void)
 		}
 	}
 
-	for (i=1;i<sysconf.hc_possible_num;i++) {
+	for (i = 1; i < sysconf.hc_possible_num; i++) {
 		if (!(sysconf.pci1234[i] & 1)) {
 			sysconf.pci1234[i] = 0;
 			sysconf.hcdn[i] = 0x20202020;
diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c
index 9603223ba3..226d9a8c0a 100644
--- a/src/northbridge/amd/amdfam10/ht_config.c
+++ b/src/northbridge/amd/amdfam10/ht_config.c
@@ -56,7 +56,7 @@ void set_config_map_reg(struct bus *link)
 	tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3;
 	tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8);
 
-	for (i=0; i < sysconf.nodes; i++) {
+	for (i = 0; i < sysconf.nodes; i++) {
 		device_t dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
 	}
@@ -67,7 +67,7 @@ void clear_config_map_reg(struct bus *link)
 	u32 i;
 	u32 ht_c_index = get_ht_c_index(link);
 
-	for (i=0; i < sysconf.nodes; i++) {
+	for (i = 0; i < sysconf.nodes; i++) {
 		device_t dev = __f1_dev[i];
 		pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
 	}
@@ -86,13 +86,13 @@ static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo)
 {
 	u32 ht_c_index = 0;
 
-	for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
+	for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) {
 		if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) {
 			return ht_c_index;
 		}
 	}
 
-	for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
+	for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) {
 		if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) {
 			 return ht_c_index;
 		}
@@ -127,7 +127,7 @@ u32 get_io_addr_index(u32 nodeid, u32 linkn)
 {
 	u32 index;
 
-	for (index=0; index<256; index++) {
+	for (index = 0; index < 256; index++) {
 		if (sysconf.conf_io_addrx[index+4] == 0) {
 			sysconf.conf_io_addr[index+4] =  (nodeid & 0x3f)  ;
 			sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
@@ -142,7 +142,7 @@ u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
 {
 	u32 index;
 
-	for (index=0; index<64; index++) {
+	for (index = 0; index < 64; index++) {
 		if (sysconf.conf_mmio_addrx[index+8] == 0) {
 			sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
 			sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
@@ -185,7 +185,7 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
 	val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used
 	sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit
 
-	if ( sysconf.mmio_addr_num<(index+1))
+	if (sysconf.mmio_addr_num<(index+1))
 		sysconf.mmio_addr_num = index+1;
 }
 
@@ -198,10 +198,10 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 
 	/* io range allocation */
 	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) |  ((io_max&0xf0)<<(12-4)); //limit
-	for (i=0; i<sysconf.nodes; i++)
+	for (i = 0; i < sysconf.nodes; i++)
 		pci_write_config32(__f1_dev[i], reg+4, tempreg);
 
-	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+	tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
 #if 0
 	// FIXME: can we use VGA reg instead?
 	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
@@ -213,7 +213,7 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 		tempreg |= PCI_IO_BASE_NO_ISA;
 	}
 #endif
-	for (i=0; i<sysconf.nodes; i++)
+	for (i = 0; i < sysconf.nodes; i++)
 		pci_write_config32(__f1_dev[i], reg, tempreg);
 }
 
@@ -224,9 +224,9 @@ void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min,
 
 	/* io range allocation */
 	tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
-	for (i=0; i<nodes; i++)
+	for (i = 0; i < nodes; i++)
 		pci_write_config32(__f1_dev[i], reg+4, tempreg);
 	tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
-	for (i=0; i<sysconf.nodes; i++)
+	for (i = 0; i < sysconf.nodes; i++)
 		pci_write_config32(__f1_dev[i], reg, tempreg);
 }
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 42647b1e3a..6ff343c578 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -65,7 +65,7 @@ static device_t __f0_dev[FX_DEVS];
 device_t __f1_dev[FX_DEVS];
 static device_t __f2_dev[FX_DEVS];
 static device_t __f4_dev[FX_DEVS];
-static unsigned fx_devs=0;
+static unsigned fx_devs = 0;
 
 device_t get_node_pci(u32 nodeid, u32 fn)
 {
@@ -605,9 +605,8 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
 			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
 				link->secondary,link->subordinate);
 			/* We need to make sure the vga_pri is under the link */
-			if ((vga_pri->bus->secondary >= link->secondary ) &&
-				(vga_pri->bus->secondary <= link->subordinate )
-			)
+			if ((vga_pri->bus->secondary >= link->secondary) &&
+			    (vga_pri->bus->secondary <= link->subordinate))
 #endif
 			break;
 		}
@@ -719,7 +718,7 @@ static void amdfam10_domain_read_resources(device_t dev)
 		if ((base & 3) != 0) {
 			unsigned nodeid, reg_link;
 			device_t reg_dev;
-			if (reg<0xc0) { // mmio
+			if (reg < 0xc0) { // mmio
 				nodeid = (limit & 0xf) + (base&0x30);
 			} else { // io
 				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
@@ -879,7 +878,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
 		 */
 		if (mem_hole.node_id==-1) {
 			resource_t limitk_pri = 0;
-			for (i=0; i<sysconf.nodes; i++) {
+			for (i = 0; i < sysconf.nodes; i++) {
 				struct dram_base_mask_t d;
 				resource_t base_k, limit_k;
 				d = get_dram_base_mask(i);
@@ -982,11 +981,11 @@ static void amdfam10_domain_set_resources(device_t dev)
 //		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
 
 		/* split the region to accommodate pci memory space */
-		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+		if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
 			if (basek <= mmio_basek) {
 				unsigned pre_sizek;
 				pre_sizek = mmio_basek - basek;
-				if (pre_sizek>0) {
+				if (pre_sizek > 0) {
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
@@ -1348,7 +1347,7 @@ static void sysconf_init(device_t dev) // first node
 
 	unsigned ht_c_index;
 
-	for (ht_c_index=0; ht_c_index<32; ht_c_index++) {
+	for (ht_c_index = 0; ht_c_index < 32; ht_c_index++) {
 		sysconf.ht_c_conf_bus[ht_c_index] = 0;
 	}
 
@@ -1369,7 +1368,7 @@ static void sysconf_init(device_t dev) // first node
 	{
 		sysconf.enabled_apic_ext_id = 1;
 	}
-	#if (CONFIG_APIC_ID_OFFSET>0)
+	#if (CONFIG_APIC_ID_OFFSET > 0)
 	if (sysconf.enabled_apic_ext_id) {
 		if (sysconf.bsp_apicid == 0) {
 			/* bsp apic id is not changed */
@@ -1492,7 +1491,7 @@ static void cpu_bus_scan(device_t dev)
 					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
 					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
-					while (dev_mc){
+					while (dev_mc) {
 						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
 						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
@@ -1516,7 +1515,7 @@ static void cpu_bus_scan(device_t dev)
 	nodes = sysconf.nodes;
 
 #if CONFIG_CBB && (NODE_NUMS > 32)
-	if (nodes>32) { // need to put node 32 to node 63 to bus 0xfe
+	if (nodes > 32) { // need to put node 32 to node 63 to bus 0xfe
 		if (pci_domain->link_list && !pci_domain->link_list->next) {
 			struct bus *new_link = new_link(pci_domain);
 			pci_domain->link_list->next = new_link;
@@ -1556,7 +1555,7 @@ static void cpu_bus_scan(device_t dev)
 		devn = CONFIG_CDB+i;
 		pbus = dev_mc->bus;
 #if CONFIG_CBB && (NODE_NUMS > 32)
-		if (i>=32) {
+		if (i >= 32) {
 			busn--;
 			devn-=32;
 			pbus = pci_domain->link_list->next;
@@ -1637,7 +1636,7 @@ static void cpu_bus_scan(device_t dev)
 			jj = cores_found;
 		}
 
-		for (j = 0; j <=jj; j++ ) {
+		for (j = 0; j <=jj; j++) {
 			u32 apic_id;
 
 			if (dual_node) {
@@ -1664,7 +1663,7 @@ static void cpu_bus_scan(device_t dev)
 				}
 			}
 
-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
+#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)
 			if (sysconf.enabled_apic_ext_id) {
 				if (apic_id != 0 || sysconf.lift_bsp_apicid) {
 					apic_id += sysconf.apicid_offset;
diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h
index 7c7065df66..bfc0da0238 100644
--- a/src/northbridge/amd/amdfam10/raminit.h
+++ b/src/northbridge/amd/amdfam10/raminit.h
@@ -17,7 +17,7 @@
 #define RAMINIT_H
 
 #if 0
-#if CONFIG_DIMM_SUPPORT==0x0110
+#if CONFIG_DIMM_SUPPORT == 0x0110
 //FBDIMM REG
 /* each channel can have 8 fbdimm */
 #define DIMM_SOCKETS 8
@@ -38,7 +38,7 @@ struct mem_controller {
 #endif
 #endif
 
-//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004
+//#if (CONFIG_DIMM_SUPPORT & 0x00ff) == 0x0004
 //DDR2 REG and unbuffered : Socket F 1027 and AM3
 /* every channel have 4 DDR2 DIMM for socket F
  *		       2 for socket M2/M3
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 6d063ab522..86f0788c46 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -524,7 +524,7 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8
 	return freq;
 }
 
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
 #include "amdfam10.h"
 #include "../amdmct/wrappers/mcti.h"
 #include "../amdmct/amddefs.h"
@@ -633,7 +633,7 @@ int mctRead_SPD(u32 smaddr, u32 reg)
 void mctSMBhub_Init(u32 node)
 {
 	struct sys_info *sysinfo = &sysinfo_car;
-	struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
+	struct mem_controller *ctrl = &(sysinfo->ctrl[node]);
 	activate_spd_rom(ctrl);
 }
 
@@ -642,9 +642,9 @@ void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 {
 	int j;
 	struct sys_info *sysinfo = &sysinfo_car;
-	struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
+	struct mem_controller *ctrl = &(sysinfo->ctrl[node]);
 
-	for (j=0;j<DIMM_SOCKETS;j++) {
+	for (j = 0; j < DIMM_SOCKETS; j++) {
 		pDCTstat->DIMMAddr[j*2] = ctrl->spd_addr[j] & 0xff;
 		pDCTstat->DIMMAddr[j*2+1] = ctrl->spd_addr[DIMM_SOCKETS + j] & 0xff;
 	}
diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
index df3850b87f..0461323666 100644
--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
@@ -56,7 +56,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
 	int j;
 	int index = 0;
 	struct mem_controller *ctrl;
-	for (i=0;i<controllers; i++) {
+	for (i = 0; i < controllers; i++) {
 		ctrl = &ctrl_a[i];
 		ctrl->node_id = i;
 		ctrl->f0 = NODE_PCI(i, 0);
@@ -70,7 +70,7 @@ static void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const
 
 		ctrl->spd_switch_addr = spd_addr[index++];
 
-		for (j=0; j < 8; j++) {
+		for (j = 0; j < 8; j++) {
 			ctrl->spd_addr[j] = spd_addr[index++];
 
 		}
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index bdf70b56b2..7ddf93f120 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -116,8 +116,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
 		if ((config_map & 3) != 3) {
 			continue;
 		}
-		if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8) )
-			) == val )
+		if ((config_map & (((63 & 0x0f)<<4) | ((63 & 0x30)<< (12-4)) | ((7 & 0x07)<<8))
+			) == val)
 		{
 			return (config_map >> 16) & 0xff;
 		}
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 6de7a8c698..7e71cf787b 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -72,9 +72,9 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
 		if (IS_ENABLED(RES_DEBUG))
 			printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 				i/4, register_values[i],
-				register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
+				register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 				register_values[i+2],
-				register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
+				register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
 				);
 		switch (register_values[i]) {
 		case RES_PCI_IO: //PCI
-- 
cgit v1.2.3