From 160ad6aa75eccf3e15bac3ccc99f5fc4cb36251d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 30 Oct 2015 18:53:48 -0500 Subject: northbridge/amd/amdfam10: Update RAM speed table with DDR3 values Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdfam10/northbridge.c | 45 +++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 13 deletions(-) (limited to 'src/northbridge/amd/amdfam10/northbridge.c') diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e44c45f0b2..2846ed3015 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -946,19 +946,38 @@ static int amdfam10_get_smbios_data16(int* count, int handle, unsigned long *cur static uint16_t amdmct_mct_speed_enum_to_mhz(uint8_t speed) { - switch (speed) { - case 1: - return 200; - case 2: - return 266; - case 3: - return 333; - case 4: - return 400; - case 5: - return 533; - default: - return 0; + if (IS_ENABLED(CONFIG_DIMM_DDR2)) { + switch (speed) { + case 1: + return 200; + case 2: + return 266; + case 3: + return 333; + case 4: + return 400; + case 5: + return 533; + default: + return 0; + } + } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + switch (speed) { + case 3: + return 333; + case 4: + return 400; + case 5: + return 533; + case 6: + return 667; + case 7: + return 800; + default: + return 0; + } + } else { + return 0; } } -- cgit v1.2.3