From 16a3a7515a65940698ec0325b6d89d5f7c40ca3c Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 3 Sep 2015 17:43:52 -0500 Subject: cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/12065 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/amd/amdfam10/misc_control.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/northbridge/amd/amdfam10/misc_control.c') diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 0b312b1c95..4c65bca79f 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -75,6 +75,7 @@ static void mcf3_read_resources(device_t dev) static void set_agp_aperture(device_t dev, uint32_t pci_id) { + uint32_t dword; struct resource *resource; resource = probe_resource(dev, 0x94); @@ -105,6 +106,11 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id) /* Report the resource has been stored... */ report_resource_stored(pdev, resource, " "); + + /* Errata 540 workaround */ + dword = pci_read_config32(pdev, 0x90); + dword |= 0x1 << 6; /* DisGartTblWlkPrb = 0x1 */ + pci_write_config32(pdev, 0x90, dword); } } } -- cgit v1.2.3