From ffcac3eb502bbe0acbb30d6fe804f00e07461a7a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 15:46:49 +0100 Subject: nb/amd/fam10: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/northbridge/amd/amdfam10/link_control.c | 153 ---------------------------- 1 file changed, 153 deletions(-) delete mode 100644 src/northbridge/amd/amdfam10/link_control.c (limited to 'src/northbridge/amd/amdfam10/link_control.c') diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c deleted file mode 100644 index 384772374b..0000000000 --- a/src/northbridge/amd/amdfam10/link_control.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2016 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Configure various power control registers, including processor - * boost support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "amdfam10.h" - -static void nb_control_init(struct device *dev) -{ - uint8_t enable_c_states; - uint8_t enable_cc6; - uint32_t dword; - - printk(BIOS_DEBUG, "NB: Function 4 Link Control.. "); - - /* Configure L3 Power Control */ - dword = pci_read_config32(dev, 0x1c4); - dword |= (0x1 << 8); /* L3PwrSavEn = 1 */ - pci_write_config32(dev, 0x1c4, dword); - - if (is_fam15h()) { - /* Configure L3 Control 2 */ - dword = pci_read_config32(dev, 0x1cc); - dword &= ~(0x7 << 6); /* ImplRdProjDelayThresh = 0x2 */ - dword |= (0x2 << 6); - pci_write_config32(dev, 0x1cc, dword); - - /* Configure TDP Accumulator Divisor Control */ - dword = pci_read_config32(dev, 0x104); - dword &= ~(0xfff << 2); /* TdpAccDivRate = 0xc8 */ - dword |= (0xc8 << 2); - dword &= ~0x3; /* TdpAccDivVal = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x104, dword); - - /* Configure Sample and Residency Timers */ - dword = pci_read_config32(dev, 0x110); - dword &= ~0xfff; /* CSampleTimer = 0x1 */ - dword |= 0x1; - pci_write_config32(dev, 0x110, dword); - - /* Configure APM TDP Control */ - dword = pci_read_config32(dev, 0x16c); - dword |= (0x1 << 4); /* ApmTdpLimitIntEn = 1 */ - pci_write_config32(dev, 0x16c, dword); - - /* Enable APM */ - dword = pci_read_config32(dev, 0x15c); - dword |= (0x1 << 7); /* ApmMasterEn = 1 */ - pci_write_config32(dev, 0x15c, dword); - - enable_c_states = 0; - enable_cc6 = 0; -#if CONFIG(HAVE_ACPI_TABLES) - uint8_t nvram; - - if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) - enable_c_states = !!nvram; - - if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) - enable_cc6 = !!nvram; -#endif - - if (enable_c_states) { - /* Configure C-state Control 1 */ - dword = pci_read_config32(dev, 0x118); - dword |= (0x1 << 24); /* PwrGateEnCstAct1 = 1 */ - dword &= ~(0x7 << 21); /* ClkDivisorCstAct1 = 0x0 */ - dword &= ~(0x3 << 18); /* CacheFlushTmrSelCstAct1 = 0x1 */ - dword |= (0x1 << 18); - dword |= (0x1 << 17); /* CacheFlushEnCstAct1 = 1 */ - dword |= (0x1 << 16); /* CpuPrbEnCstAct1 = 1 */ - dword &= ~(0x1 << 8); /* PwrGateEnCstAct0 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct0 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x2 */ - dword |= (0x2 << 2); - dword |= (0x1 << 1); /* CacheFlushEnCstAct0 = 1 */ - dword |= 0x1; /* CpuPrbEnCstAct0 = 1 */ - pci_write_config32(dev, 0x118, dword); - - /* Configure C-state Control 2 */ - dword = pci_read_config32(dev, 0x11c); - dword &= ~(0x1 << 8); /* PwrGateEnCstAct2 = 0 */ - dword &= ~(0x7 << 5); /* ClkDivisorCstAct2 = 0x0 */ - dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x0 */ - dword &= ~(0x1 << 1); /* CacheFlushEnCstAct0 = 0 */ - dword &= ~(0x1); /* CpuPrbEnCstAct0 = 0 */ - pci_write_config32(dev, 0x11c, dword); - - /* Configure C-state Policy Control 1 */ - dword = pci_read_config32(dev, 0x128); - dword &= ~(0x7f << 5); /* CacheFlushTmr = 0x28 */ - dword |= (0x28 << 5); - dword &= ~0x1; /* CoreCstateMode = !enable_cc6 */ - dword |= ((enable_cc6)?0:1); - pci_write_config32(dev, 0x128, dword); - } - } - - printk(BIOS_DEBUG, "done.\n"); -} - - -static struct device_operations mcf4_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nb_control_init, - .scan_bus = 0, - .ops_pci = 0, -}; - -static const struct pci_driver mcf4_driver_fam10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1204, -}; - -static const struct pci_driver mcf4_driver_fam15_model10 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1404, -}; - -static const struct pci_driver mcf4_driver_fam15 __pci_driver = { - .ops = &mcf4_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1604, -}; -- cgit v1.2.3