From 64f6b71af5443ac4e1126dc5f5202a1bc8657b31 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:16:56 +0200 Subject: src/northbridge: Fix typo Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/amdfam10/amdfam10.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/northbridge/amd/amdfam10/amdfam10.h') diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index b744e96562..5102b0bb30 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -314,7 +314,7 @@ struct MCTStatStruc; // for 0x98 index and 0x9c data for DCT0 // for 0x198 index and 0x19c data for DCT1 -// even at ganged mode, 0x198/0x19c will be used for channnel B +// even at ganged mode, 0x198/0x19c will be used for channel B #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98 #define DCAO_DctOffset_SHIFT 0 @@ -368,9 +368,9 @@ struct MCTStatStruc; #define DODCC_ProcOdt_75_OHMS 2 /* - for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs - for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 + for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of all DIMMs + for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] control timing of DIMM0 + F2x[1,0]9C_x[102:101], [103], [106:105], [107] control timing of DIMM1 So Socket F with Four Logical DIMM will only support DDR2 800 ? */ /* there are index +100 ===> for DIMM1 -- cgit v1.2.3