From 61be3603f4b9f353e605d7b7c8d0d9f3b90f5636 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 15 Apr 2017 20:07:53 +0300 Subject: AGESA: Fix UMA calculations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode decides already in AMD_INIT_POST the exact location of UMA memory. To meet alignment requirements, it will extend uma_memory_size. We cannot calculate base from size and TOP_MEM1, but need to calculate size from base and TOP_MEM1 instead. Also allows selection of UmaMode==UMA_SPECIFIED to manually set amount of memory reserved for framebuffer. Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/19328 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marshall Dawson --- src/northbridge/amd/agesa/agesawrapper.c | 3 ++ src/northbridge/amd/agesa/family12/northbridge.c | 43 +------------------ src/northbridge/amd/agesa/family14/northbridge.c | 40 +---------------- src/northbridge/amd/agesa/family15/northbridge.c | 47 +------------------- src/northbridge/amd/agesa/family15rl/northbridge.c | 47 +------------------- src/northbridge/amd/agesa/family15tn/northbridge.c | 47 +------------------- src/northbridge/amd/agesa/family16kb/northbridge.c | 50 +--------------------- 7 files changed, 9 insertions(+), 268 deletions(-) (limited to 'src/northbridge/amd/agesa') diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index efacaff9e9..079625671a 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include @@ -110,6 +111,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) status = AmdInitPost(PostParams); AGESA_EVENTLOG(status, &PostParams->StdHeader); + backup_top_of_ram(PostParams->MemConfig.Sub4GCacheTop); + AmdReleaseStruct(&AmdParamStruct); return status; diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 668e1bb3e1..c931bf09a0 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -422,34 +422,6 @@ static void set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family12h BKDG. */ - /* Please reference MemNGetUmaSizeLN () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { - uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ - } else if (sys_mem >= 0x40000000) { - uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ - } else { - uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - /* Domain/Root Complex related code */ static void domain_read_resources(device_t dev) @@ -514,7 +486,6 @@ static void domain_set_resources(device_t dev) unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -595,8 +566,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -612,17 +581,10 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) @@ -811,11 +773,8 @@ static void root_complex_enable_dev(struct device *dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b35599e186..e5700963d8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -458,31 +458,6 @@ static void domain_read_resources(device_t dev) pci_domain_read_resources(dev); } -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family14h BKDG. */ - sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() - if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { - uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ - } - else { - if (sys_mem >= 0x40000000) { - uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ - } else { - uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ - } - } - - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); @@ -490,7 +465,6 @@ static void domain_set_resources(device_t dev) unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -576,8 +550,6 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -594,17 +566,10 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) { @@ -836,11 +801,8 @@ static void root_complex_enable_dev(struct device *dev) { static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 77db0543e2..5cb0f91f33 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -699,43 +699,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 - -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeOR () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 64 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - - static void domain_set_resources(device_t dev) { unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -806,8 +773,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -824,16 +789,9 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) { @@ -1095,11 +1053,8 @@ static void root_complex_enable_dev(struct device *dev) { static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index c87ef482db..aa24a6af40 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -695,43 +695,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 - -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeOR () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 64 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - - static void domain_set_resources(struct device *dev) { unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -804,8 +771,6 @@ static void domain_set_resources(struct device *dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -823,16 +788,9 @@ static void domain_set_resources(struct device *dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) { @@ -1085,11 +1043,8 @@ static void root_complex_enable_dev(struct device *dev) { static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c8909fb009..95787fc867 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -694,43 +694,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 - -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeOR () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 64 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); -#endif -} - - static void domain_set_resources(device_t dev) { unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -801,8 +768,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -820,16 +785,9 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) { @@ -1082,11 +1040,8 @@ static void root_complex_enable_dev(struct device *dev) { static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 5b475fe4e8..f91448afc8 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -709,45 +709,10 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 - -static void setup_uma_memory(void) -{ -#if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family16h BKDG. */ - /* Please reference MemNGetUmaSizeOR () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sys_mem >= 1024 << ONE_MB_SHIFT) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 64 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ -#endif -} - - static void domain_set_resources(device_t dev) { unsigned long mmio_basek; u32 pci_tolm; - u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -806,7 +771,6 @@ static void domain_set_resources(device_t dev) idx += 0x10; basek = (8*64)+(16*16); sizek = limitk - ((8*64)+(16*16)); - } //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); @@ -820,8 +784,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -839,16 +801,9 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; } -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif + add_uma_resource_below_tolm(dev, 7); for (link = dev->link_list; link; link = link->next) { if (link->children) { @@ -1101,11 +1056,8 @@ static void root_complex_enable_dev(struct device *dev) { static int done = 0; - /* Do not delay UMA setup, as a device on the PCI bus may evaluate - the global uma_memory variables already in its enable function. */ if (!done) { setup_bsp_ramtop(); - setup_uma_memory(); done = 1; } -- cgit v1.2.3