From 3d3152eec7efe9bf02499c42b92b4ad22bd7fd4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 10 Jan 2019 09:05:30 +0200 Subject: AGESA: Drop CONFIG_CBB and CONFIG_CDB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Static values, copy paste from multi-node fam15 code. Add header that shall have declarations of functions common to different families factored out. Change-Id: I07bc046c74280f49e46793c119d36b87b8789949 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30732 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 5 +++-- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 5 +++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 11 ++++++----- src/northbridge/amd/agesa/family16kb/northbridge.c | 11 ++++++----- src/northbridge/amd/agesa/nb_common.h | 19 +++++++++++++++++++ 7 files changed, 39 insertions(+), 16 deletions(-) create mode 100644 src/northbridge/amd/agesa/nb_common.h (limited to 'src/northbridge/amd/agesa') diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 0e5dc3c14a..9fd6547aa5 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -27,7 +27,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); + dev = PCI_DEV(0, DEV_CDB, 1); #else dev = __f1_dev[0]; #endif // defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index a290eff268..21d8fb4196 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -33,6 +33,7 @@ #include "sb_cimx.h" +#include #include #include @@ -46,7 +47,7 @@ static unsigned fx_devs = 0; static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -89,7 +90,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam12_nodeid(struct device *dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } #include "amdfam12_conf.c" diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index 0eabaa8842..9248e6f0b8 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -27,7 +27,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) struct device *dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); + dev = PCI_DEV(0, DEV_CDB, 1); #else dev = __f1_dev[0]; #endif // defined(__PRE_RAM__) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index adf7878859..296f40a412 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -43,7 +44,7 @@ static unsigned fx_devs = 0; static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -85,7 +86,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam14_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } #include "amdfam14_conf.c" diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index f1a2051233..edc4585c70 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -99,7 +100,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -142,7 +143,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -818,9 +819,9 @@ static void cpu_bus_scan(struct device *dev) int siblings = 0; unsigned int family; - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -843,7 +844,7 @@ static void cpu_bus_scan(struct device *dev) unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cf7e3f86a6..da54fd8052 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -98,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); } static void get_fx_devs(void) @@ -141,7 +142,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev) int siblings = 0; unsigned int family; - dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev) unsigned devn; struct bus *pbus; - devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus; /* Find the cpu's pci device */ diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h new file mode 100644 index 0000000000..3e78155afd --- /dev/null +++ b/src/northbridge/amd/agesa/nb_common.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_NB_COMMON_H__ +#define __AMD_NB_COMMON_H__ + +#define DEV_CDB 0x18 + +#endif -- cgit v1.2.3