From 27ed80bce1da2d17fecd342a8150f790939150a1 Mon Sep 17 00:00:00 2001
From: Bruce Griffith <Bruce.Griffith@se-eng.com>
Date: Fri, 15 Aug 2014 11:46:25 -0600
Subject: AMD Steppe Eagle: Add northbridge files for new SoC family

Add the northbridge file for AMD's new Mullins and Steppe Eagle
processor family.  Since the processor family name is not the
same across AMD's sales and marketing channels, I have elected
to use part of the processor ID as the family name.  The intent
is to reduce confusion since the processor ID is the same for
both families.  This northbridge support has only been validated
on the AMD Embedded variants ("Steppe Eagle").

The AGESA wrappers in coreboot have a function that is intended to
mirror the UMA memory allocation performed during memory initialization
by AGESA.  Update the Steppe Eagle memory allocation to mimic the
memory reservation done inside the AGESA BLOB.

Change the default CBMEM address, the default video BIOS device ID,
and a couple of other defaults to match changes in coreboot community
code.

The northbridge chip.h specifies how many processor sockets, how
many channels, and how many DIMM slots are supported by the
northbridge.  Steppe Eagle does not permit multisocket systems
and has only one memory controller channel.

Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6678
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
---
 .../amd/agesa/00730F01/acpi/northbridge.asl        | 100 +++++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl

(limited to 'src/northbridge/amd/agesa/00730F01/acpi')

diff --git a/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl b/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl
new file mode 100644
index 0000000000..37aba9a2ea
--- /dev/null
+++ b/src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
+Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */
+{
+	Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+	Return(0x0B)	/* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+	If(PMOD)
+	{
+		Return(APR0)	/* APIC mode */
+	}
+	Return (PR0)		/* PIC Mode */
+}
+
+Device(AMRT) {
+	Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Gpp 0 */
+Device(PBR4) {
+	Name(_ADR, 0x00020001)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS4) }	/* APIC mode */
+		Return (PS4)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR4 */
+
+/* Gpp 1 */
+Device(PBR5) {
+	Name(_ADR, 0x00020002)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS5) }	/* APIC mode */
+		Return (PS5)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR5 */
+
+/* Gpp 2 */
+Device(PBR6) {
+	Name(_ADR, 0x00020003)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS6) }	/* APIC mode */
+		Return (PS6)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR6 */
+
+/* Gpp 3 */
+Device(PBR7) {
+	Name(_ADR, 0x00020004)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS7) }	/* APIC mode */
+		Return (PS7)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR7 */
+
+/* Gpp 4 */
+Device(PBR8) {
+	Name(_ADR, 0x00020005)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS8) }	/* APIC mode */
+		Return (PS8)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */
-- 
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