From fd440bb79eedf36fdd27d26801146a2ecb5218a3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Aug 2017 08:30:43 +0200 Subject: mb/asrock/g41c-gs: Fix the SATA clock output on ck505 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With reset default of the clockgen on this board the SATA clock which needs to be 100MHz depends on FSB BSEL straps. This explains why SATA was originally tested to be working but fails with CPUs operating at different FSB. This change sets a bit in the clockgen configuration which fixes the SATA clock. TESTED on with a 1333MHz FSB CPU. Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21257 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Jonathan Neuschäfer --- src/mainboard/asrock/g41c-gs/Kconfig | 1 + src/mainboard/asrock/g41c-gs/devicetree.cb | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig index 62cd7e9dfe..e65f4eef6b 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig +++ b/src/mainboard/asrock/g41c-gs/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME + select DRIVERS_I2C_CK505 config MAINBOARD_DIR string diff --git a/src/mainboard/asrock/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/devicetree.cb index fd7f271339..f58fae749c 100644 --- a/src/mainboard/asrock/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/devicetree.cb @@ -140,6 +140,12 @@ chip northbridge/intel/x4x # Northbridge end device pci 1f.3 on # SMbus subsystemid 0x1849 0x27da + chip drivers/i2c/ck505 # W83115RG-965 + # set SATA to fixed 100Mhz refclk + register "mask" = "{ 0x02 }" + register "regs" = "{ 0x02 }" + device i2c 69 on end + end end device pci 1f.4 off end device pci 1f.5 off end -- cgit v1.2.3