From fb2f667da2091ce2194274f95c2d5db024d46e63 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 Mar 2017 11:50:10 +0200 Subject: nb/amd/amdk8: Link raminit_f.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For this debug.c needs to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/amd/dbm690t/romstage.c | 8 +++----- src/mainboard/amd/mahogany/romstage.c | 8 +++----- src/mainboard/amd/pistachio/romstage.c | 8 +++----- src/mainboard/amd/serengeti_cheetah/romstage.c | 9 ++++----- src/mainboard/asrock/939a785gmh/romstage.c | 7 +++---- src/mainboard/asus/a8n_e/romstage.c | 8 ++++---- src/mainboard/asus/a8v-e_deluxe/romstage.c | 7 +++---- src/mainboard/asus/a8v-e_se/romstage.c | 7 +++---- src/mainboard/asus/k8v-x/romstage.c | 7 +++---- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 12 +++++------- src/mainboard/asus/m2n-e/romstage.c | 9 ++++----- src/mainboard/asus/m2v-mx_se/romstage.c | 9 ++++----- src/mainboard/asus/m2v/romstage.c | 9 ++++----- src/mainboard/broadcom/blast/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 9 ++++----- src/mainboard/gigabyte/m57sli/romstage.c | 8 +++----- src/mainboard/hp/dl145_g1/romstage.c | 8 ++++---- src/mainboard/hp/dl145_g3/romstage.c | 9 ++++----- src/mainboard/iwill/dk8_htx/romstage.c | 8 ++++---- src/mainboard/kontron/kt690/romstage.c | 9 ++++----- src/mainboard/msi/ms7135/romstage.c | 8 ++++---- src/mainboard/msi/ms7260/romstage.c | 9 ++++----- src/mainboard/msi/ms9185/romstage.c | 9 ++++----- src/mainboard/msi/ms9282/romstage.c | 9 ++++----- src/mainboard/nvidia/l1_2pvv/romstage.c | 9 ++++----- src/mainboard/siemens/sitemp_g1p1/romstage.c | 8 +++----- src/mainboard/sunw/ultra40/romstage.c | 8 ++++---- src/mainboard/sunw/ultra40m2/romstage.c | 9 ++++----- src/mainboard/supermicro/h8dme/romstage.c | 9 ++++----- src/mainboard/supermicro/h8dmr/romstage.c | 9 ++++----- src/mainboard/technexion/tim5690/romstage.c | 9 ++++----- src/mainboard/technexion/tim8690/romstage.c | 9 ++++----- src/mainboard/tyan/s2912/romstage.c | 9 ++++----- src/mainboard/winent/mb6047/romstage.c | 7 +++---- 34 files changed, 127 insertions(+), 161 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 89456404bd..0e21475c8f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -33,22 +33,20 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #include #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 55771f9b1e..b22dec19ee 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -33,17 +33,16 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include #include -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #include unsigned get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } @@ -51,7 +50,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/rs780/early_setup.c" #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index a8242ec837..8578cd1a3a 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -31,20 +31,18 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */ #include -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 5e0123b5b4..9fac7cf0f9 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -26,7 +26,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -44,9 +44,9 @@ static void memreset_setup(void) outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -60,7 +60,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 0894af9e53..1894fdefb9 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -34,7 +34,6 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include #include -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -42,10 +41,10 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index d10fe9aaac..f58729d433 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -38,7 +38,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -46,10 +46,10 @@ #include #include -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c6ea08da26..04edc7e8b2 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include #include #include -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include #include "northbridge/amd/amdk8/setup_resource_map.c" #include @@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus); #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index f2465d03c8..fb3bb57229 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include #include #include -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include #include "northbridge/amd/amdk8/setup_resource_map.c" #include @@ -48,10 +47,10 @@ unsigned int get_sbdn(unsigned bus); #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index a0565a9ce7..83194fc3e9 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,6 @@ unsigned int get_sbdn(unsigned bus); #include #include #include -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include #include "northbridge/amd/amdk8/setup_resource_map.c" #include @@ -46,10 +45,10 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index d7bebbb702..c38164e12b 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -44,11 +44,9 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } - -static void activate_spd_rom(const struct mem_controller *ctrl); +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -56,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -181,7 +178,8 @@ static const uint16_t spd_addr[] = { RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 91fded1e05..7bf8306813 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -36,7 +36,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) @@ -55,10 +55,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} -static inline void activate_spd_rom(const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} +void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 8aea021081..25eedbabeb 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -46,10 +46,10 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index e8053424e3..3b6990b2c5 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,7 +34,7 @@ unsigned int get_sbdn(unsigned bus); #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -48,10 +48,10 @@ unsigned int get_sbdn(unsigned bus); #define IT8712F_GPIO_BASE 0x0a20 -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index a67ae46066..b618b52049 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -13,7 +13,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -24,16 +24,16 @@ unsigned get_sbdn(unsigned bus); static void memreset_setup(void) { } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_HUB, device); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 337423fbd8..0414df1142 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -37,17 +37,17 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -55,7 +55,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index da96ed70c5..c58b526e9b 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -34,7 +34,6 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) @@ -53,10 +52,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -75,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 46831322e8..5420df13ef 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -16,7 +16,7 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -39,7 +39,7 @@ static void memreset_setup(void) } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -51,7 +51,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { int ret,i; unsigned device=(ctrl->channel0[0])>>8; @@ -76,7 +76,7 @@ static inline void change_i2c_mux(unsigned device) printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index e7a3b2f36e..6ccaf95d92 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -39,7 +39,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) @@ -47,9 +47,9 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -58,7 +58,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a31ecefbaa..9723ad2277 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "northbridge/amd/amdk8/debug.c" + #include #include #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -39,7 +39,7 @@ static void memreset_setup(void) } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -49,9 +49,9 @@ static void memreset(int controllers, const struct mem_controller *ctrl) } } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 8a01e6b317..55ac1bcabb 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -38,17 +38,16 @@ #include "southbridge/amd/sb600/early_setup.c" #include -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 25c4a403ef..1da2ff4d3c 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -35,7 +35,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -49,10 +49,10 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index d1c50df33f..35c8943676 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -36,7 +36,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) @@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} -static inline void activate_spd_rom(const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} +void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index db5242926a..141c7e0fd3 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -45,9 +45,9 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -56,7 +56,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 463a7679d0..afb82eba72 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,7 +32,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -55,9 +55,9 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -66,7 +66,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index ac070e9925..9ae0ed4397 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -35,7 +35,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) @@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 15ba45f1b1..4411368704 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -40,31 +40,29 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #include #define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { } /* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { } /*called in raminit_f.c */ -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index a1659b7f84..7df486a438 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -15,7 +15,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include "superio/smsc/lpc47b397/early_gpio.c" @@ -26,7 +26,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -40,9 +40,9 @@ static void sio_gpio_setup(void) } #endif -static inline void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 6c3fdbd4e6..576ca6b562 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -34,7 +34,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) @@ -52,10 +52,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -64,7 +64,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index fdfb124fcb..60c38454a2 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -32,7 +32,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -51,9 +51,9 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #if 0 /* We don't do any switching yet. */ @@ -65,7 +65,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #endif } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -74,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 89cea08a9a..bc0a3ec0da 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -35,7 +35,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -54,10 +54,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -66,7 +66,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e534617e4d..4ffafb11df 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -38,17 +38,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index d5a4784ced..7f41536277 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include #include #include @@ -39,17 +39,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 02b4680287..97655aab80 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -35,7 +35,7 @@ #include #include #include -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -53,10 +53,10 @@ unsigned get_sbdn(unsigned bus) return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 2fe96a7f8c..327e592c83 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -15,7 +15,6 @@ #include #include #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" #include #include #include @@ -25,10 +24,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset_setup(void) { } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } -- cgit v1.2.3