From f8f9b282b4f7ce2f6b83005db0f9aa5cf3f810ec Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Thu, 30 Apr 2020 12:47:25 -0700 Subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/romstage.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index 94af1b6dfe..0d1ccabfea 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,8 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + void *start = (void *) m_cfg; + + // BoardId + write8(start + 140, 0x1d); + + // BoardTypeBitmask + write32(start + 104, 0x11111111); + + // DebugPrintLevel + write8(start + 45, 8); + + // KtiLinkSpeedMode + write8(start + 64, 0); + + // KtiPrefetchEn + write8(start + 53, 2); } -- cgit v1.2.3