From f8b237b28df43c6cb58d1ca8eb61bc483a327f8c Mon Sep 17 00:00:00 2001
From: Karthikeyan Ramasubramanian <kramasub@google.com>
Date: Wed, 16 Jun 2021 17:37:38 -0600
Subject: mb/google/guybrush: Add devfn macros for devices on GPP bridge

Add devfn macros for some peripheral devices that are attached to PCIE
GPP Bridge.

BUG=None
TEST=Build and boot to OS in Guybrush.

Change-Id: I7c5433dff2329f13c282908e2b848405819347ff
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/mainboard/google/guybrush/port_descriptors.c   | 26 ++++++++++++----------
 .../baseboard/include/baseboard/variants.h         |  6 +++++
 2 files changed, 20 insertions(+), 12 deletions(-)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index 540d3d19a7..489bccdec0 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <baseboard/variants.h>
+#include <device/pci_def.h>
 #include <soc/platform_descriptors.h>
 #include <soc/gpio.h>
 #include <types.h>
@@ -11,8 +13,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 0,
 		.end_logical_lane = 0,
-		.device_number = 2,
-		.function_number = 1,
+		.device_number = PCI_SLOT(WLAN_DEVFN),
+		.function_number = PCI_FUNC(WLAN_DEVFN),
 		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ0,
@@ -24,8 +26,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 1,
 		.end_logical_lane = 1,
-		.device_number = 2,
-		.function_number = 2,
+		.device_number = PCI_SLOT(SD_DEVFN),
+		.function_number = PCI_FUNC(SD_DEVFN),
 		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ1,
@@ -37,8 +39,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 2,
 		.end_logical_lane = 2,
-		.device_number = 2,
-		.function_number = 3,
+		.device_number = PCI_SLOT(WWAN_DEVFN),
+		.function_number = PCI_FUNC(WWAN_DEVFN),
 		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ2,
@@ -50,8 +52,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 4,
 		.end_logical_lane = 7,
-		.device_number = 2,
-		.function_number = 4,
+		.device_number = PCI_SLOT(NVME_DEVFN),
+		.function_number = PCI_FUNC(NVME_DEVFN),
 		.link_aspm = ASPM_L1,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ3,
@@ -63,8 +65,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 8,
 		.end_logical_lane = 11,
-		.device_number = 2,
-		.function_number = 5,
+		.device_number = PCIE_GPP_BRIDGE_2_DEV,
+		.function_number = PCIE_GPP_2_4_FUNC,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ5,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@@ -74,8 +76,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.port_present = true,
 		.start_logical_lane = 16,
 		.end_logical_lane = 23,
-		.device_number = 1,
-		.function_number = 1,
+		.device_number = PCIE_GPP_BRIDGE_1_DEV,
+		.function_number = PCIE_GPP_1_0_FUNC,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ6,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index 37ee241017..6b82d183d7 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -4,6 +4,12 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <amdblocks/gpio_banks.h>
+#include <soc/pci_devs.h>
+
+#define WLAN_DEVFN	PCIE_GPP_2_0_DEVFN
+#define SD_DEVFN	PCIE_GPP_2_1_DEVFN
+#define WWAN_DEVFN	PCIE_GPP_2_2_DEVFN
+#define NVME_DEVFN	PCIE_GPP_2_3_DEVFN
 
 /*
  * This function provides base GPIO configuration table. It is typically provided by
-- 
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