From f82758a8762ffb1df8fafed5769dfbbd63cc216e Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Fri, 10 Jul 2015 17:09:37 +0530 Subject: Glados: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Wenkai Du Original-Tested-by: Wenkai Du Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel --- src/mainboard/google/glados/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 206086667b..6f89063ffb 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/skylake [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + [PchSerialIoIndexUart2] = PchSerialIoPci, \ }" # Enable Root port 1 and 5. -- cgit v1.2.3