From f8042458f789a6cb583802319b9bcd49bad66ed7 Mon Sep 17 00:00:00 2001 From: Terry Chen Date: Tue, 3 May 2022 18:23:25 +0800 Subject: mb/google/brya/var/crota: setting for codec reset pin Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/crota/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index a5464552f4..35803a0242 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -22,8 +22,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> NC */ PAD_NC(GPP_B3, NONE), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC(GPP_B15, NONE), + /* B15 : PROC_GP3 ==> AUD_RST_L */ + PAD_CFG_GPO(GPP_B15, 1, PWROK), /* C3 : GPP_C3 ==> SML0_SMBCLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -- cgit v1.2.3