From f7a0ba84dcddf08cdd6a4431c899ae1ee0ed986c Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 19 Jun 2003 15:14:52 +0000 Subject: - Update the romcc version. - Add an additional consistency check to romcc and fix the more obvious problems it has uncovered With this update there are no known silent failures in romcc. - Update the memory initialization code to setup all 3 of the memory sizing registers properly - In auto.c test our dynamic maximum amount of ram. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/solo/auto.c | 3 +-- src/mainboard/amd/solo/failover.c | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/solo/auto.c b/src/mainboard/amd/solo/auto.c index f61b794256..94ce39d464 100644 --- a/src/mainboard/amd/solo/auto.c +++ b/src/mainboard/amd/solo/auto.c @@ -177,7 +177,6 @@ static void main(void) print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\r\n"); -#warning "FIXME if I pass msr.lo somehow I get the value 0x00000030 as stop in ram_check" - ram_check(0x00000000, 0x20000000); + ram_check(0x00000000, msr.lo); } } diff --git a/src/mainboard/amd/solo/failover.c b/src/mainboard/amd/solo/failover.c index cda8ea8076..da0f1d0302 100644 --- a/src/mainboard/amd/solo/failover.c +++ b/src/mainboard/amd/solo/failover.c @@ -7,8 +7,6 @@ #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" - - static void main(void) { if (do_normal_boot()) { -- cgit v1.2.3