From f48faa06c946696e4845e569b7ecf995015bbeb6 Mon Sep 17 00:00:00 2001 From: EricKY Cheng Date: Mon, 24 Oct 2022 15:08:16 +0800 Subject: mb/google/skyrim/var/winterhold: Update DPTC setting for SMT Follow Dynamic Thermal Table Switching proposal to initialize thermal table config E as default table for SMT. Since the dynamic thermal table switching mechanism is still under cooking, after discussing with thermal team, suggest adopting config E(limit Soc not reach to max power) as default thermal config to avoid any thermal-related issue during phase build. Once the dynamic thermal table switching mechanism is finished, will change the default value to config A. BUG=b:232946420, b:258572474 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68742 Tested-by: build bot (Jenkins) Reviewed-by: Jon Murphy Reviewed-by: Dtrain Hsu --- .../skyrim/variants/winterhold/overridetree.cb | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 78a8091ceb..38a9d7c62f 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -1,6 +1,31 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip soc/amd/mendocino + + register "system_configuration" = "4" + + # TODO : Set DPTC confiuration. Table E (SMT) + # TODO : Table E as default is only for SMT + # TODO : This needs to be cleaned up before b/232946420 can be resolved + # TODO : Here is the separate thread number b/258572474 for Table E (SMT) + register "thermctl_limit_degreeC" = "97" + register "fast_ppt_limit_mW" = "22000" + register "slow_ppt_limit_mW" = "15000" + register "slow_ppt_time_constant_s" = "4" + register "sustained_power_limit_mW" = "12000" + + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "7000" + register "stt_m1" = "0x114" + register "stt_m2" = "0x371" + register "stt_c_apu" = "0xE333" + register "stt_alpha_apu" = "0x6666" + register "stt_skin_temp_apu" = "0x3000" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller -- cgit v1.2.3