From f32a533931845f7974b25dda7191eac40ef831e5 Mon Sep 17 00:00:00 2001 From: John Su Date: Wed, 8 Jun 2022 16:35:18 +0800 Subject: mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0 The TBT device can't be recognized after we re-plug it at DB type-c port. Intel found that tbt_pcie_rp0 has mapping error after each re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this problem and take this as short term solution. Intel will implement re-mapping mechanism in ACPI for long term solution. BUG=b:230141802 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su Change-Id: I61429033dfe64d67916167bb901bdd8246db953e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/felwinter/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 0a44186d70..06b351800c 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -181,7 +181,7 @@ chip soc/intel/alderlake device generic 0 alias dptf_policy on end end end - device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on probe DB_USB USB4_KB8001 end -- cgit v1.2.3