From f15f310ea4af0d9db5f2b0dd5daac0fb8967e25f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 12:04:42 +0100 Subject: mb/lenovo/t420/devicetree: Use subsystemid inheritance Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/t420/devicetree.cb | 50 +++++++++------------------------ 1 file changed, 14 insertions(+), 36 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 6deff6039c..53bd16f68a 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -37,13 +37,11 @@ chip northbridge/intel/sandybridge register "pci_mmio_size" = "2048" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end # host bridge + subsystemid 0x17aa 0x21ce inherit + + device pci 00.0 on end # host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x21ce - end # Integrated Graphics Controller + device pci 02.0 on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -67,6 +65,7 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" + register "c2_latency" = "101" # c2 not supported # device specific SPI configuration @@ -77,46 +76,30 @@ chip northbridge/intel/sandybridge device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 on - subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device pci 1a.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x21ce - end # High Definition Audio Controller + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB Enhanced Host Controller #2 + device pci 1b.0 on end # High Definition Audio Controller device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on - subsystemid 0x17aa 0x21ce - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on - subsystemid 0x17aa 0x21ce smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 on - subsystemid 0x17aa 0x21ce chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" - device pci 00.0 on - subsystemid 0x17aa 0x21ce - end + device pci 00.0 on end end end # PCIe Port #5 (Ricoh SD & FW) device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on - subsystemid 0x17aa 0x21ce - end # USB Enhanced Host Controller #1 + device pci 1d.0 on end # USB Enhanced Host Controller #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x21ce chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end + device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" end @@ -176,11 +159,8 @@ chip northbridge/intel/sandybridge register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x21ce - end # 6 port SATA AHCI Controller + device pci 1f.2 on end # 6 port SATA AHCI Controller device pci 1f.3 on - subsystemid 0x17aa 0x21ce # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -194,9 +174,7 @@ chip northbridge/intel/sandybridge end end # SMBus Controller device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on - subsystemid 0x17aa 0x21ce - end # Thermal + device pci 1f.6 on end # Thermal end end end -- cgit v1.2.3