From e8c655dd1b2490e24640ebafb16120e5e9c268f3 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Tue, 2 Apr 2019 18:55:15 +0530 Subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp This patch configures FSP UPD values for HPD and DDC of DDI ports for CMLRVP. BUG=none TEST= Tested that eDP works on CMLRVP. Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140 Reviewed-by: Furquan Shaikh Reviewed-by: Maulik V Vaghela Tested-by: build bot (Jenkins) --- .../intel/coffeelake_rvp/variants/cml_u/devicetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb index 6484330ae1..241ac33345 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -10,6 +10,19 @@ chip soc/intel/cannonlake register "HeciEnabled" = "1" register "s0ix_enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- cgit v1.2.3