From e781856af1d68318c2d876ebb9daa7e68db0ae01 Mon Sep 17 00:00:00 2001 From: kane_chen Date: Fri, 31 Aug 2018 17:38:07 +0800 Subject: mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0. On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/rammus/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 78de3caba8..0e8ce4d042 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -203,6 +203,10 @@ chip soc/intel/skylake .sda_hold = 36, }, }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, }" # Touchscreen -- cgit v1.2.3