From e5eaa4b5a5dfaf7081d5656823c5bf428e9b8648 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 1 Feb 2018 00:39:53 -0600 Subject: google/lars: update device properties for Nuvoton codec Adapted from Chromium commit: 848ee3a [Lars: Add device properties for Nuvoton codec] Update sar-threshold, sar-compare-time, sar-sampling-time properties to match values in lars' Chromium branch. Adaptation needed to account for parameters having moved from mainboard.asl to devicetree in upstream tree. Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90 Original-Signed-off-by: David Wu Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Benson Leung Original-Tested-by: David Wu Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/23567 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/lars/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 99522cbe3e..64f2a61f97 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -233,14 +233,14 @@ chip soc/intel/skylake register "vref_impedance" = "2" # 125kOhm register "micbias_voltage" = "6" # 2.754 register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0a" - register "sar_threshold[1]" = "0x14" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" register "sar_threshold[2]" = "0x26" register "sar_threshold[3]" = "0x73" register "sar_hysteresis" = "0" register "sar_voltage" = "6" - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us register "short_key_debounce" = "3" # 30ms register "jack_insert_debounce" = "7" # 512ms register "jack_eject_debounce" = "0" -- cgit v1.2.3