From e4ac7b16efcdadadae80b4e6feb4f37601dec5ed Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 26 Oct 2023 19:36:00 +0530 Subject: mb/google/rex/var/screebo: Set Baseline Power Limit This patch allows google/rex mainboard to choose between "Performance" (PL_PERFORMANCE) and "Baseline" (PL_BASELINE) power limits (PLs). This is important for platform to meet balance between power and performance. The OEM design google/screebo selects baseline power limit to maintain the balance performance in lower power. BUG=b:307237761 TEST=Able to build and boot google/screebo. w/o this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 57 Watts [INFO ] CPU PL4 = 114 Watts w/ this patch: screebo4es-rev1 ~ # cbmem -c -1 | grep "CPU PL" [INFO ] CPU PL1 = 15 Watts [INFO ] CPU PL2 = 40 Watts [INFO ] CPU PL4 = 84 Watts Change-Id: I43debc5442ae9c01851652beba676ffc102ca27d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/78661 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai --- src/mainboard/google/rex/Kconfig | 13 +++++++ .../google/rex/variants/baseboard/rex/ramstage.c | 44 ++++++++++++++++++++++ .../google/rex/variants/screebo/overridetree.cb | 6 +++ 3 files changed, 63 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index e781f08597..c162a44473 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -238,4 +238,17 @@ config USE_PM_ACPI_TIMER config HAVE_SLP_S0_GATE def_bool n +choice + prompt "Choose desired processor power limits (PLs)" + default PL_BASELINE if BOARD_GOOGLE_MODEL_SCREEBO + default PL_PERFORMANCE + +config PL_PERFORMANCE + bool "Performance: Maximum PLs for maximum performance" + +config PL_BASELINE + bool "Baseline: Baseline PLs for balanced performance at lower power" + +endchoice + endif # BOARD_GOOGLE_REX_COMMON diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index d2adaaee52..02bdca5d01 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -10,6 +10,7 @@ * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) * Following values are for performance config as per document #640982 */ +#if CONFIG(PL_PERFORMANCE) const struct cpu_tdp_power_limits performance_efficient_limits[] = { { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, @@ -51,6 +52,49 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = { .pl4_power = 64000 }, }; +#else +const struct cpu_tdp_power_limits performance_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits power_optimized_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; +#endif void variant_devtree_update(void) { diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 06f7b9bcea..0d69aca25a 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -34,6 +34,12 @@ end chip soc/intel/meteorlake + register "power_limits_config[MTL_P_282_242_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 40, + .tdp_pl4 = 84, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 -- cgit v1.2.3