From e3bf8ba2d812dd027afa8ee8ff368a5295ce1bda Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 7 Apr 2020 23:34:12 -0700 Subject: mb/google/volteer: Enable RP LTR setting BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 361e563cab..ab911d2173 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,20 +43,24 @@ chip soc/intel/tigerlake # Enable NVMe PCIE 9 using clk 0 register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "1" # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" # Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" -- cgit v1.2.3