From e3229a5192a84c04a4d1f0307d8cfb5e864b7ff3 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Thu, 13 Feb 2020 15:34:24 +0000 Subject: mb/amd/olivehill: Switch away from ROMCC_BOOTBLOCK Warning: not tested on hardware. Signed-off-by: Mike Banon Change-Id: If8dd531db4a4a16ad7a068ceb281a01f4f245386 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38867 Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/amd/olivehill/Kconfig | 4 --- src/mainboard/amd/olivehill/Kconfig.name | 4 +-- src/mainboard/amd/olivehill/Makefile.inc | 2 ++ src/mainboard/amd/olivehill/bootblock.c | 29 ++++++++++++++++++++ src/mainboard/amd/olivehill/romstage.c | 46 -------------------------------- 5 files changed, 33 insertions(+), 52 deletions(-) create mode 100644 src/mainboard/amd/olivehill/bootblock.c delete mode 100644 src/mainboard/amd/olivehill/romstage.c (limited to 'src/mainboard') diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 78f768f132..bd3dd9384c 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_OLIVEHILL - def_bool n - if BOARD_AMD_OLIVEHILL config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehill/Kconfig.name b/src/mainboard/amd/olivehill/Kconfig.name index d065472731..fd1a713aac 100644 --- a/src/mainboard/amd/olivehill/Kconfig.name +++ b/src/mainboard/amd/olivehill/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_AMD_OLIVEHILL -# bool"Olive Hill" +config BOARD_AMD_OLIVEHILL + bool "Olive Hill" diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index f8895faa92..4dde2cfd1e 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehill/bootblock.c b/src/mainboard/amd/olivehill/bootblock.c new file mode 100644 index 0000000000..d1f8d606e4 --- /dev/null +++ b/src/mainboard/amd/olivehill/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + int i; + u32 val; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +} diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c deleted file mode 100644 index dfe7c49f9f..0000000000 --- a/src/mainboard/amd/olivehill/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -void board_BeforeAgesa(struct sysinfo *cb) -{ - int i; - u32 val; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - pm_io_write8(0xd2, 0); - - /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - pm_io_write8(0xea, 1); - - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - for (i = 0; i < 200000; i++) - val = inb(0xcd6); -} -- cgit v1.2.3