From da79f5c91d94883589a3530f4cc30231a9826bf0 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Thu, 25 Apr 2019 12:06:23 -0700 Subject: mb/google/sarien: Add psys_pmax setting to 136W This patch adds the setting of psys_pmax to 136W. According to the design, Rpsys is 11.8Kohm. Here is the equation to come out the Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm / 2 = 1.2V Hence, Psys_pmax is 136W. BUG=b:124792558 BRANCH=None TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is passed to FSP by enabling FSP log & Boot into the OS Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056 Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/32457 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 96146baf1e..7dd9f154ef 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -43,6 +43,7 @@ chip soc/intel/cannonlake register "SlowSlewRateForFivr" = "2" register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "51" + register "psys_pmax" = "136" register "Device4Enable" = "1" # Enable eDP device register "DdiPortEdp" = "1" -- cgit v1.2.3