From d5d56b3d42efeeebde9a8867d95e21d7b698aa18 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 4 Jan 2023 12:10:23 -0700 Subject: mb/system76/tgl-u: Leave TBT LSX0 as FSP configured Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/mainboard/system76/tgl-u/variants/darp7/gpio.c | 4 ++-- src/mainboard/system76/tgl-u/variants/galp5/gpio.c | 4 ++-- src/mainboard/system76/tgl-u/variants/lemp10/gpio.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c index ad18ca6483..3e0bc7743c 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/gpio.c @@ -137,8 +137,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E15, NONE), // ALERT# PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) PAD_NC(GPP_E20, NONE), // SWI# PAD_NC(GPP_E21, NONE), // DDP2 I2C / TBT_LSX1 strap PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c index 17119b3e75..7b8e850d8f 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c @@ -131,8 +131,8 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_E15, NONE), // ALERT#_R PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) PAD_NC(GPP_E20, NONE), PAD_NC(GPP_E21, NONE), PAD_NC(GPP_E22, NONE), diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c index cca2056450..cd9f833e94 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/gpio.c @@ -131,8 +131,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_E15, DN_20K, DEEP), // SCI# _PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000), // SMI# PAD_NC(GPP_E17, NONE), - PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 - PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016) + // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016) _PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000), // SWI# PAD_NC(GPP_E21, NONE), // GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V) PAD_NC(GPP_E22, NONE), -- cgit v1.2.3