From d1f9d73efc7cf6dda522c8eb984a95335883a7da Mon Sep 17 00:00:00 2001 From: Jianjun Wang Date: Wed, 17 Apr 2024 10:53:29 +0800 Subject: mb/google/rauru: Add PCIe domain support Add PCIe domain support. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/mainboard/google/rauru/devicetree.cb | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rauru/devicetree.cb b/src/mainboard/google/rauru/devicetree.cb index d2288f4a09..df65b3f24b 100644 --- a/src/mainboard/google/rauru/devicetree.cb +++ b/src/mainboard/google/rauru/devicetree.cb @@ -2,4 +2,23 @@ chip soc/mediatek/mt8196 device cpu_cluster 0 on end + + device domain 0 on + register "pcie_config" = "{ + .base = 0x16940000, + .mmio_res_io = { + .cpu_addr = 0x58000000, + .pci_addr = 0x58000000, + .size = 16 * MiB, + .type = IORESOURCE_IO, + }, + .mmio_res_mem = { + .cpu_addr = 0x59000000, + .pci_addr = 0x59000000, + .size = 64 * MiB, + .type = IORESOURCE_MEM, + }, + }" + device pci 00.0 on end # - Host Bridge + end end -- cgit v1.2.3