From cec52453b7d6dc48d3f004be73e49f84c327d54b Mon Sep 17 00:00:00 2001 From: Mathew King Date: Tue, 16 Mar 2021 12:49:26 -0600 Subject: mb/google/guybrush: Configure UART0 gpio in early stage BUG=b:180721208 TEST=builds Signed-off-by: Mathew King Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai --- src/mainboard/google/guybrush/variants/baseboard/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 21fc420866..9b8df52dfb 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -166,6 +166,10 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), /* ESPI_ALERT_L */ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), }; /* GPIO configuration for sleep */ -- cgit v1.2.3