From cb5323415e5eaa7aabc7f4e359274562cab131e3 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 11 Jan 2019 13:46:18 -0800 Subject: mb/intel/coffeelake_rvp: Update mainboard UART Kconfig Update mainboard UART Kconfig for Whiskylake RVP. TEST=Build and test on Whiskylake RVP. By default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port2. Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled. Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e Signed-off-by: Wonkyu Kim Reviewed-on: https://review.coreboot.org/c/30861 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/mainboard/intel/coffeelake_rvp/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 9474c513b2..95eeeff284 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE if BOARD_INTEL_WHISKEYLAKE_RVP select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select DRIVERS_I2C_HID @@ -48,6 +49,11 @@ config MAX_CPUS default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 default 8 +config UART_FOR_CONSOLE + int + default 2 if BOARD_INTEL_WHISKEYLAKE_RVP + default 0 + config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -- cgit v1.2.3