From caa85f249d5f8be09ecd7b03e9e87a2fac0190dc Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Wed, 20 Feb 2019 15:05:33 +0530 Subject: soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all DDI ports are enabled and hence configures the HPD and CLK for DDI ports. This patch initializes only the required UPDs to enable display ports. BUG=b:123907904 TEST=DP devices working correctly. Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 +++++ src/mainboard/google/sarien/variants/arcada/devicetree.cb | 7 +++++++ src/mainboard/google/sarien/variants/sarien/devicetree.cb | 7 +++++++ 3 files changed, 19 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 16a0ef134f..0299ded7b5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -66,6 +66,11 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "15" register "tdp_pl2_override" = "44" register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 5e70481bff..6f167c208c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -41,6 +41,13 @@ chip soc/intel/cannonlake register "SlowSlewRateForGt" = "0" register "SlowSlewRateForSa" = "0" register "SlowSlewRateForFivr" = "0" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index df22affcd9..2714b60155 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -45,6 +45,13 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + # Enable DDC for DDI port B + register "DdiPortBDdc" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ -- cgit v1.2.3