From c86fa6d97584ce941d847c1eabf388a226ba2638 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 17 Feb 2017 17:26:04 -0800 Subject: google/eve: Set rise/fall timing values for I2C bus 1 Apply the measured rise and fall times for I2C bus 1 on Eve so it can be tuned properly for 400KHz operation. BUG=chrome-os-partner:63020 TEST=verify I2C1 bus speed with a scope Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/18396 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/eve/devicetree.cb | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index dfe7281d8d..c600b5fde2 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -168,8 +168,12 @@ chip soc/intel/skylake register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio # Enable I2C1 bus early for TPM access - register "i2c[1].early_init" = "1" - register "i2c[1].speed" = "I2C_SPEED_FAST" + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 32, + }" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ -- cgit v1.2.3