From c5b9658961ec24991c727b8873534b7d38760dcb Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Mon, 19 Jun 2017 20:47:27 -0400 Subject: purism/librem13v2: Update devicetree settings Disable SataDevSlp and update other values to match vendor/AMI firmware. Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd Signed-off-by: Youness Alaoui Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/22042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/purism/librem13v2/devicetree.cb | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 29d35afd23..76a0f7ebaf 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -3,8 +3,8 @@ chip soc/intel/skylake # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration @@ -32,7 +32,10 @@ chip soc/intel/skylake register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" register "EnableAzalia" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" @@ -55,7 +58,7 @@ chip soc/intel/skylake register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" @@ -150,10 +153,6 @@ chip soc/intel/skylake # Enable Root Ports 5 and 9 register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# for RP9 - register "PcieRpClkReqSupport[8]" = "1" - # ClkReq for NVMe - Bruteforced (no other value works) - register "PcieRpClkReqNumber[8]" = "2" register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) -- cgit v1.2.3